1. Field of the Invention
The present invention relates to DLL (Delayed Locked Loop) circuits effective for use in a semiconductor integrated circuit, particularly to a DLL circuit of high reliability.
2. Description of the Background Art
A conventional DLL circuit 200 that provides consistency between the phase of a delay clock and the phase of a reference clock includes a control clock generation circuit 210, a phase comparator 220, a filter 230, a counter control circuit 240, a counter 250 and a delay circuit 260, as shown in FIG. 21. Control clock generation circuit 210 receives a reference clock CLK from an IN terminal to generate control clocks SET and CNT.
Referring to FIG. 22, phase comparator 220 includes NOR gates 221 and 223, NAND gates 226, 227, 229 and 231-234, shift registers 222 and 224, and inverters 225 and 228. Phase comparator 220 multiplies reference clock CLK and delay clock CLKD by 2 to generate respective multiplied reference clock CLK2 and delay clock CLKD2 and compares the phase of multiplied delay clock CLKD2 with the phase of multiplied reference clock CLK2. The comparison result is output from an UP terminal. It is to be noted that a DN terminal is not used.
Filter 230 is driven in synchronization with reference clock CLK to generate and output signals PUP and PDN according to the comparison result from phase comparator 220.
With reference to FIG. 23, counter control circuit 240 includes inverters 241-243, a NOR gate 244, and shift registers 245 and 246. Counter control circuit 240 is driven in synchronization with control clock SET from control clock generation circuit 210 to generate a counter control signal ADD and a signal EN with signals PUP and PDN generated by filter 230 as input signals according to the comparison result of phase comparator 220.
Counter 250 is driven in synchronization with control clock CNT from control clock generation circuit 210 to count up/down according to input signals ADD and EN from counter control circuit 240 to generate addresses a0-a5. At this stage, counter 250 counts up and down when signal ADD is at an H level (logical high) and an L level (logical low), respectively, with signal EN as an input signal. Delay circuit 260 delays reference clock CLK by a predetermined amount to output delay clock CLKD according to addresses a0-a5 from counter 250.
Delay circuit 260 delays reference clock CLK by a predetermined amount according to addresses a0-a5 from counter 250 to output delay clock CLKD.
In DLL circuit 200, a counter control signal ADD that controls the count of counter 250 is generated according to the comparison result between the phase of delay clock CLKD and the phase of reference clock CLK. Count is effected up/down according to the generated counter control signal ADD to provide addresses a0-a5. The phase of reference clock CLK is delayed according to addresses a0-a5, and the phase of delay clock CLKD is made to be consistent with the phase of reference clock CLK.
The reason why phase comparator 220 compares the phase of delay clock CLKD2 corresponding to delay clock CLKD multiplied by 2 with the phase of reference clock CLK2 corresponding to reference clock CLK multiplied by 2 is to prevent the comparison result from attaining an L level at each rise of reference clock CLK2, as shown in FIG. 24, to suppress erroneous operation of DLL circuit 200.
Since phase comparator 220 forming conventional DLL circuit 200 compares the phases of reference clock CLK and delay clock CLKD after they are multiplied, the L level cycle of multiplied delay clock CLKD2 becomes longer when one component 251 in delay clock CLKD is missing, as shown in FIG. 25. There was problem that the comparison result attains an L level at the rise of reference clock CLK2, whereby DLL circuit 200 operates erroneously.
Counter control circuit 240 forming conventional DLL circuit 200 employs the structure of generating counter control signal ADD and signal EN according to signals PUP and PDN output from filter 230. If a frequency-multiply circuit is not used, the comparison result will attain an L level when addresses a0-a5 output from counter 250 take the smallest values, whereby counter control signal ADD and signal EN will be generated to cause counter 250 to count down. As a result, there was a problem that counter 250 cannot generate addresses a0-a5 properly.
In view of the foregoing, an object of the present invention is to provide a DLL circuit that can have the phase of delay clock CLKD coincide with the phase of reference clock CLK stably when reset is effected or when phase comparison of the delay clock with respect to reference clock exhibits an L level with addresses a0-a5 taking the smallest values.
According to an aspect of the present invention, a DLL circuit includes a control clock generation circuit generating a first control clock according to a reference clock and a second control clock having a phase difference with respect to the first control clock, a phase comparator comparing the phase of the delay clock with the phase of the reference clock, a filter providing a control signal applied with weight corresponding to the comparison result of the phase comparator, a counter control circuit driven in synchronization with the first control clock to generate a counter control signal according to the control signal, a counter driven in synchronization with the second control clock to count up/down according to the counter control signal to provide first and second addresses and a smallest address signal activated when the first and second addresses take the smallest values and setting the address to the smallest value in response to a reset signal, a first delay circuit generating first and second signals having a predetermined phase difference according to a reference clock and generating a fine adjustment clock whose phase is present between the phase of the first signal and the phase of the second signal according to the generated first and second signals and first address, and a second delay circuit delaying the fine adjustment clock by an integral multiple of a predetermined amount to output a delay dock according to the second address. The counter control circuit outputs a counter control signal activated to force the counter to count up when a reset signal is input or when an activated smallest address signal and an output signal of a filter that causes the counter to count down are input.
According to the DLL circuit of the present invention, a counter control signal controlling the count of the counter is generated according to the comparison result between the phase of the delay clock and the phase of the reference clock. The counter counts up/down according to the generated counter control signal to generate first and second addresses. A fine adjustment dock is generated with the phase of the reference clock CLK delayed within a range of a predetermined amount T according to the first address. A delay clock is generated delaying the fine adjustment dock by an integral multiple of the predetermined amount T according to the second address. When a reset signal is input, or when the comparison result of the phase comparator provides an L level in the case where the first and second addresses take the smallest values, the counter is forced to count up. Therefore, first and second addresses can be generated properly even when reset, or when the comparison result of the phase comparator provides an L level in the case where the address takes the smallest value. Accordingly, the phase can be set in phase precisely. Furthermore, the delay clock can be set in phase with the reference clock at the high accuracy of within a predetermined amount T.
Preferably, the counter control circuit generates a force up signal rendered active according to a reset signal or an output signal of the filter that causes the counter to count down, and renders the counter control signal active according to the generated force up signal.
In the DLL circuit, the counter proceeds to the force up mode when a reset signal or a control signal corresponding to the comparison result of an L level is applied to the counter control circuit. Therefore, the first and second addresses can be generated always correctly.
Preferably, the counter control circuit renders the force up signal inactive at the elapse of two cycles of the first control clock after the output of the filter that causes the counter to count up is rendered active.
In the DLL circuit, the force up mode is canceled at the elapse of two cycles of the first control clock after the comparison result of the phase comparator attains an H level. Thus, in response to a reset signal or a control signal corresponding to a comparison result of an L level, the force up mode is promptly entered and then canceled promptly after the counter counts up.
Preferably, the first delay circuit generates a fine adjustment clock by applying weight to the first and second signals according to the first address.
The first delay circuit applies weight on the first and second signals having a phase difference of a predetermined amount T according to the first address and generates a fine adjustment clock whose phase is present between the phase of the first signal and the phase of the second signal. Therefore, the phase of the delay clock can be made to match the phase of the reference dock at a high accuracy of within a predetermined amount T.
Preferably, the first delay circuit includes a first inverter circuit that applies weight to the first signal by determining the size, and a second inverter circuit having an output terminal connected to the output terminal of the first inverter circuit to apply weight to the second signal by determining the size. The counter provides a first address to determine the size of the first and second inverter circuits to the first delay circuit.
In the first delay circuit, the size of the first and second inverter circuits are determined according to the first address from the counter. Weight is applied to the first and second signals having a phase difference of a predetermined amount T according to the determined size. Therefore, weight can be easily applied to the first and second signals by using an inverter whose size is variable. As a result, the phase of the reference dock can be adjusted in high accuracy within the range of a predetermined amount T.
Preferably, the first delay circuit includes a plurality of first inverters connected in parallel, each having a different size, and a plurality of second inverters of different sizes connected in parallel, and having an output terminal connected to the output terminal of the plurality of first inverters. The counter provides a first address to the first delay circuit to selectively render the first and second inverters active.
In the first delay circuit, a portion of the plurality of first and second inverters having different sizes and connected in parallel is selectively rendered active according to the first address from the counter. Then, weight is applied to the first and second signals having the phase difference of a constant amount T.
Weight can be easily applied to the first and second signals by just connecting inverters of different sizes in parallel. As a result, the phase of the reference clock can be adjusted at high accuracy within the range of a predetermined amount T.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.